Start the IP core generation workflow.Ģ.1. You can then integrate the generated IP core with a larger FPGA embedded design in the Intel Qsys environment.Ģ. HDL Coder packages all the generated files into an IP core folder.
QUARTUS ADD DEVICE SUPPORT CODE
HDL Coder generates HDL code from the Simulink blocks, and also generates HDL code for the AXI interface logic connecting the IP core to the embedded processor. Using the IP Core Generation workflow in the HDL Workflow Advisor enables you to automatically generate a sharable and reusable IP core module from a Simulink model. Generate an HDL IP core using the HDL Workflow Advisorġ.
QUARTUS ADD DEVICE SUPPORT REGISTRATION
The following code describes the contents of a DE1-SoC reference design registration file containing the reference design plugin DE1SoCRegistration.qsys_base_170 associated with the board Terasic DE1-SoC development Kit. A reference design registration file must also contain the name of the associated board. Create a reference design registration file named hdlcoder_ref_design_customization.m containing a list of reference design plugins associated with an SoC board.Ī reference design plugin is a MATLAB package folder containing the reference design definition file and all files associated with the SoC design project. In this section, we outline the steps necessary to register the custom reference design in HDL Workflow Advisor.ġ. Register the custom reference design in HDL Workflow Advisor
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